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INTEGRATED CIRCUITS
74ABT16841A 74ABTH16841A 20-bit bus interface latch (3-State)
Product specification Supersedes data of 1995 Sep 28 IC23 Data Handbook 1998 Feb 27
Philips Semiconductors
Philips Semiconductors
Product specification
20-bit bus interface latch (3-State)
74ABT16841A 74ABTH16841A
FEATURES
* High speed parallel latches * Live insertion/extraction permitted * Extra data width for wide address/data paths or buses carrying * Power-up 3-State * 74ABTH16841A incorporates bus-hold data inputs which
eliminate the need for external pull-up resistors to hold unused inputs parity
DESCRIPTION
The 74ABT16841A Bus interface latch is designed to provide extra data width for wider data/address paths of buses carrying parity. The 74ABT16841A consists of two sets of ten D-type latches with 3-State outputs. The flip-flops appear transparent to the data when Latch Enable (nLE) is High. This allows asynchronous operation, as the output transition follows the data in transition. On the nLE High-to-Low transition, the data that meets the setup and hold time is latched. Data appears on the bus when the Output Enable (nOE) is Low. When nOE is High the output is in the High-impedance state. Two options are available, 74ABT16841A which does not have the bus-hold feature and 74ABTH16841A which incorporates the bus-hold feature.
* Power-up reset * Ideal where high speed, light loading, or increased fan-in are * Output capability: +64mA/-32mA * Latch-up protection exceeds 500mA per Jedec Std 17 * ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model required with MOS microprocessors
QUICK REFERENCE DATA
SYMBOL tPLH tPHL CIN COUT ICCZ ICCL PARAMETER Propagation delay nDx to nQx Input capacitance Output capacitance Quiescent supply current CONDITIONS Tamb = 25C; GND = 0V CL = 50pF; VCC = 5V VI = 0V or VCC VO = 0V or VCC; 3-State Outputs disabled; VCC = 5.5V Outputs LOW; VCC = 5.5V TYPICAL 3.1 2.2 4 7 500 10 UNIT ns pF pF A mA
ORDERING INFORMATION
PACKAGES 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II 56-Pin Plastic SSOP Type III 56-Pin Plastic TSSOP Type II TEMPERATURE RANGE -40C to +85C -40C to +85C -40C to +85C -40C to +85C OUTSIDE NORTH AMERICA 74ABT16841A DL 74ABT16841A DGG 74ABTH16841A DL 74ABTH16841A DGG NORTH AMERICA BT16841A DL BT16841A DGG BH16841A DL BH16841A DGG DWG NUMBER SOT371-1 SOT364-1 SOT371-1 SOT364-1
PIN DESCRIPTION
PIN NUMBER 55, 54, 52, 51, 49, 48, 47, 45, 44, 43 42, 41, 40, 38, 37, 36, 34, 33, 31, 30 2, 3, 5, 6, 8, 9, 10, 12, 13, 14 15, 16, 17, 19, 20, 21, 23, 24, 26, 27 1, 28 56, 29 4, 11, 18, 25, 32, 39, 46, 53 7, 22, 35, 50 SYMBOL 1D0 - 1D9 2D0 - 2D9 1Q0 - 1Q9 2Q0 - 2Q9 1OE, 2OE 1LE, 2LE GND VCC Data inputs Data outputs Output enable inputs (active-Low) Latch enable inputs (active rising edge) Ground (0V) Positive supply voltage FUNCTION
1998 Feb 27
2
853-1797 19025
Philips Semiconductors
Product specification
20-bit bus interface latch (3-State)
74ABT16841A 74ABTH16841A
PIN CONFIGURATION
1OE 1Q0 1Q1 GND 1Q2 1Q3 VCC 1Q4 1Q5 1Q6 GND 1Q7 1Q8 1Q9 2Q0 2Q1 2Q2 GND 2Q3 2Q4 2Q5 VCC 2Q6 2Q7 GND 2Q8 2Q9 2OE 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 1LE 1D0 1D1 GND 1D2 1D3 VCC 1D4 1D5
LOGIC SYMBOL (IEEE/IEC)
1OE 1LE 2OE 2LE 1D0 1D1 1D2 1D3 1D4 1D6 1D5 GND 1D7 1D8 1D9 2D0 2D1 2D2 GND 2D3 2D4 2D5 VCC 2D6 2D7 GND 2D8 2D9 2LE 1D6 1D7 1D8 1D9 2D0 2D1 2D2 2D3 2D4 2D5 2D6 2D7 2D8 2D9 1 56 28 29 55 54 52 51 49 48 47 45 44 43 42 41 40 38 37 36 34 33 31 30 3D 4 EN2 C1 EN4 C3 1D 2 2 3 5 6 8 9 10 12 13 14 15 16 17 19 20 21 23 24 26 27 1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9 2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
SH00081
FUNCTION TABLE
INPUTS nOE nLE H H X nDx L H l h X OUTPUTS nQ0 - nQ9 L H L H Z OPERATING MODE
SA00076
LOGIC SYMBOL
55 54 52 51 49 48 47 45 44 43
L L L L H
Transparent Latched High impedance
1D0 1D1 1D2 1D3 1D4 1D5 1D6 56 1 1LE 1OE
1D7 1D8
1D9
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7 1Q8 1Q9
2 42
3 41
5 40
6 38
8 37
9 36
10 34
12 33
13 31
14 30
2D0 2D1 2D2 2D3 2D4 2D5 2D6 29 28 2LE 2OE
2D7 2D8
2D9
L L X NC Hold H = High voltage level h = High voltage level one set-up time prior to the High-to-Low LE transition L = Low voltage level l = Low voltage level one set-up time prior to the High-to-Low LE transition = High-to-Low LE transition NC= No change X = Don't care Z = High impedance "off" state
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7 2Q8 2Q9
15
16
17
19
20
21
23
24
26
27
SH00023
1998 Feb 27
3
Philips Semiconductors
Product specification
20-bit bus interface latch (3-State)
74ABT16841A 74ABTH16841A
LOGIC DIAGRAM
nD0 nD1 nD2 nD3 nD4 nD5 nD6 nD7 nD8 nD9
D
D
D
D
D
D
D
D
D
D
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
L
Q
nLE
nOE nQ0 nQ1 nQ2 nQ3 nQ4 nQ5 nQ6 nQ7 nQ8 nQ9
SH00024
ABSOLUTE MAXIMUM RATINGS1, 2
SYMBOL VCC IIK VI IOK VOUT IO OUT Tstg PARAMETER DC supply voltage DC input diode current DC input voltage3 VO < 0 Output in Off or High state Output in Low state DC output current Output in High state Storage temperature range -64 -65 to 150 C VI < 0 CONDITIONS RATING -0.5 to +7.0 -18 -1.2 to +7.0 -50 -0.5 to +5.5 128 mA UNIT V mA V mA V
DC output diode current DC output voltage3
NOTES: 1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability. 2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150C. 3. The input and output voltage ratings may be exceeded if the input and output current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
LIMITS SYMBOL VCC VI VIH VIL IOH IOL t/v Tamb DC supply voltage Input voltage High-level input voltage Low-level Input voltage High-level output current Low-level output current Input transition rise or fall rate Operating free-air temperature range 0 -40 PARAMETER Min 4.5 0 2.0 0.8 -32 64 5 +85 Max 5.5 VCC V V V V mA mA ns/V C UNIT
1998 Feb 27
4
Philips Semiconductors
Product specification
20-bit bus interface latch (3-State)
74ABT16841A 74ABTH16841A
DC ELECTRICAL CHARACTERISTICS
LIMITS SYMBOL PARAMETER TEST CONDITIONS Tamb = +25C Min VIK VOH VOL VRST II Input clamp voltage High-level output voltage Low-level output voltage Power-up output voltage3 Input leakage current In ut 74ABT16841A Input leakage current 74ABTH16841A Bus Hold current inputs6 74ABTH16841A Power-off leakage current Power-up/down 3-State output current4 3-State output High current 3-State output Low current Output High leakage current Output current1 Quiescent supply current Additional supply current per input pin2 VCC = 4.5V; IIK = -18mA VCC = 4.5V; IOH = -3mA; VI = VIL or VIH VCC = 5.0V; IOH = -3mA; VI = VIL or VIH VCC = 4.5V; IOH = -32mA; VI = VIL or VIH VCC = 4.5V; IOL = 64mA; VI = VIL or VIH VCC = 5.5V; IO = 1mA; VI = GND or VCC VCC = 5.5V; VI = VCC or GND VCC = 5.5V; VI = VCC or GND VCC = 5.5V; VI = VCC VCC = 5.5V; VI = 0 VCC = 4.5V; VI = 0.8V VCC = 4.5V; VI = 2.0V VCC = 5.5V; VI = 0 to 5.5V IOFF IPU/PD IOZH IOZL ICEX IO ICCH ICCL ICCZ ICC VCC = 0.0V; VO or VI 4.5V VCC = 2.1V; VO = 0.5V; VI = GND or VCC; VOE = Don't care VCC = 5.5V; VO = 2.7V; VI = VIL or VIH VCC = 5.5V; VO = 0.5V; VI = VIL or VIH VCC = 5.5V; VO = 5.5V; VI = GND or VCC VCC = 5.5V; VO = 2.5V VCC = 5.5V; Outputs High, VI = GND or VCC VCC = 5.5V; Outputs Low, VI = GND or VCC VCC = 5.5V; Outputs 3-State; VI = GND or VCC VCC = 5.5V; one input at 3.4V, other inputs at VCC or GND -50 IHOLD Control pins Data pins5 ins 35 -75 800 5.0 5.0 5.0 -5.0 5.0 -70 0.5 10 0.5 0.2 100 50 10 -10 50 -180 1 19 1 1 -50 100 50 10 -10 50 -180 1 19 1 1 A A A A A mA mA mA mA mA 2.5 3.0 2.0 Typ -0.9 2.9 3.4 2.4 0.42 0.13 0.01 0.01 0.01 -2 0.55 0.55 1 1 1 -3 35 -75 A Max -1.2 2.5 3.0 2.0 0.55 0.55 1.0 1 1 -5 Tamb = -40C to +85C Min Max -1.2 V V V V V V A A A A UNIT
II
NOTES: 1. Not more than one output should be tested at a time, and the duration of the test should not exceed one second. 2. This is the increase in supply current for each input at 3.4V. 3. For valid test results, data must not be loaded into the flip-flops (or latches) after applying the power. 4. This parameter is valid for any VCC between 0V and 2.1V with a transition time of up to 10msec. From VCC = 2.1V to VCC = 5V 10% a transition time of up to 100sec is permitted. 5. Unused pins at VCC or GND. 6. This is the bus hold overdrive current required to force the input to the opposite logic state.
AC CHARACTERISTICS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM MIN tPLH tPHL tPLH tPHL tPZH tPZL tPHZ tPLZ Propagation delay nDx to nQx Propagation delay nLE to nQx Output enable time to High and Low level Output disable time from High and Low level 2 1 4 5 4 5 1.1 1.5 1.5 1.0 1.2 1.2 1.8 1.5 Tamb = VCC = +5.0V TYP 3.1 2.2 2.5 2.1 2.4 2.2 3.0 2.5 +25oC MAX 4.1 3.1 3.3 2.8 3.2 2.9 4.0 3.2 Tamb = -40 to +85oC VCC = +5.0V 0.5V MIN 1.1 1.5 1.5 1.0 1.2 1.2 1.8 1.5 MAX 4.9 3.6 3.7 3.1 4.0 3.6 4.9 3.7 ns ns ns ns UNIT
1998 Feb 27
5
Philips Semiconductors
Product specification
20-bit bus interface latch (3-State)
74ABT16841A 74ABTH16841A
AC SETUP REQUIREMENTS
GND = 0V, tR = tF = 2.5ns, CL = 50pF, RL = 500 LIMITS SYMBOL PARAMETER WAVEFORM Tamb = +25oC VCC = +5.0V Min ts(H) ts(L) th(H) th(L) tw(H) Setup time, High or Low nDx to nLE Hold time, High or Low nDx to nLE nLE pulse width High 3 3 1 2.0 1.0 2.0 2.0 2.9 Typ 1.0 0.4 -0.3 -0.7 1.9 Tamb = -40 to +85oC VCC = +5.0V 0.5V Min 2.0 1.0 2.0 2.0 2.9 Max ns ns ns UNIT
AC WAVEFORMS
VM = 1.5V, VIN = GND to 3.0V
3.0V or VCC whichever is less 0V tw(H) tPHL nQx VM tPLH VOH VM VOL nQx VM tPZH tPHZ VOH VY 0V nOE VM VM 3.0V or VCC whichever is less 0V
nLE
VM
VM
VM
SH00007
SA00078
Waveform 1. Propagation Delay, Latch Enable Input to Output, and Enable Pulse Width
nOE 3.0V or VCC whichever is less 0V tPLH tPHL 3.0V or VCC whichever is less 0V nQx
Waveform 4. 3-State Output Enable Time to High Level and Output Disable Time from High Level
VM tPZL
VM tPLZ
3.0V or VCC whichever is less 0V
nDx INPUT
VM
VM
3.0V or VCC VM VX VOL 0V
nQx OUTPUT
VM
VM
SH00008
SA00079
Waveform 5. 3-State Output Enable Time to Low Level and Output Disable Time from Low Level
Waveform 2. Propagation Delay for Data to Outputs
nDx
VM
VM
VM
VM
3.0V or VCC whichever is less
nLE
1998 Feb 27
EEEEEEEEE EEE E EEEEEEEEE EEE E
ts(H) th(H) ts(L) th(L) VM VM NOTE: The shaded areas indicate when the input is permitted to change for predictable output performance.
0V 3.0V or VCC whichever is less
0V
SA00080
Waveform 3. Data Setup and Hold Times
6
Philips Semiconductors
Product specification
20-bit bus interface latch (3-State)
74ABT16841A 74ABTH16841A
TEST CIRCUIT AND WAVEFORM
VCC 7.0V RL 90% NEGATIVE PULSE VM 10% tTHL (tF) CL RL POSITIVE PULSE 10% tW tTLH (tR) 90% 90% VM 10% 0V 10% 0V tTLH (tR) tTHL (tF) AMP (V) tW VM 90% AMP (V)
PULSE GENERATOR
VIN D.U.T. RT
VOUT
Test Circuit for 3-State Outputs
VM
SWITCH POSITION
TEST tPLZ tPZL All other SWITCH closed closed open
VM = 1.5V Input Pulse Definition
DEFINITIONS
RL = Load resistor; see AC CHARACTERISTICS for value. CL = Load capacitance includes jig and probe capacitance; see AC CHARACTERISTICS for value. RT = Termination resistance should be equal to ZOUT of pulse generators.
INPUT PULSE REQUIREMENTS FAMILY Amplitude 74ABT/H16 3.0V Rep. Rate 1MHz tW 500ns tR 2.5ns tF 2.5ns
SA00018
1998 Feb 27
7
Philips Semiconductors
Product specification
20-bit bus interface latch (3-State)
74ABT16841A 74ABTH16841A
SSOP56: plastic shrink small outline package; 56 leads; body width 7.5 mm
SOT371-1
1998 Feb 27
8
Philips Semiconductors
Product specification
20-bit bus interface latch (3-State)
74ABT16841A 74ABTH16841A
TSSOP56: plastic thin shrink small outline package; 56 leads; body width 6.1mm
SOT364-1
1998 Feb 27
9
Philips Semiconductors
Product specification
20-bit bus interface latch (3-State)
74ABT16841A 74ABTH16841A
Data sheet status
Data sheet status Objective specification Preliminary specification Product specification Product status Development Qualification Definition [1] This data sheet contains the design target or goal specifications for product development. Specification may change in any manner without notice. This data sheet contains preliminary data, and supplementary data will be published at a later date. Philips Semiconductors reserves the right to make chages at any time without notice in order to improve design and supply the best possible product. This data sheet contains final specifications. Philips Semiconductors reserves the right to make changes at any time without notice in order to improve design and supply the best possible product.
Production
[1] Please consult the most recently issued datasheet before initiating or completing a design.
Definitions
Short-form specification -- The data in a short-form specification is extracted from a full data sheet with the same type number and title. For detailed information see the relevant data sheet or data handbook. Limiting values definition -- Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information -- Applications that are described herein for any of these products are for illustrative purposes only. Philips Semiconductors make no representation or warranty that such applications will be suitable for the specified use without further testing or modification.
Disclaimers
Life support -- These products are not designed for use in life support appliances, devices or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips Semiconductors customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips Semiconductors for any damages resulting from such application. Right to make changes -- Philips Semiconductors reserves the right to make changes, without notice, in the products, including circuits, standard cells, and/or software, described or contained herein in order to improve design and/or performance. Philips Semiconductors assumes no responsibility or liability for the use of any of these products, conveys no license or title under any patent, copyright, or mask work right to these products, and makes no representations or warranties that these products are free from patent, copyright, or mask work right infringement, unless otherwise specified. Philips Semiconductors 811 East Arques Avenue P.O. Box 3409 Sunnyvale, California 94088-3409 Telephone 800-234-7381 (c) Copyright Philips Electronics North America Corporation 1998 All rights reserved. Printed in U.S.A. print code Document order number: Date of release: 05-96 9397-750-03506
Philips Semiconductors
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